The cad/qflow port
qflow-1.4.83p4 – full end-to-end digital synthesis flow for VLSI ASIC designs
Description
A digital synthesis flow is a set of tools and methods used to turn a
VLSI design written in a high-level behavioral language like Verilog
or VHDL into a physical circuit, which can either be configuration code
for an FPGA target or a layout in a specific technology, that would
become part of an IC.
Qflow uses a complete and open source tool chain for synthesizing
digital circuits starting from Verilog source and ending in physical
layout for a specific target fabrication process.
WWW: http://opencircuitdesign.com/qflow/
- Only for arches
-
aarch64
aarch64
alpha
amd64
amd64
arm
arm
hppa
i386
i386
mips64
mips64
mips64el
mips64el
powerpc
powerpc
powerpc64
powerpc64
riscv64
riscv64
sparc64
- Categories:
-
cad
lang/python
lang/tcl
Library dependencies
Build dependencies
Run dependencies